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Preliminary GS8662S08/09/18/36E-333/300/250/200/167
165-Bump BGA Commercial Temp Industrial Temp Features
* Simultaneous Read and Write SigmaSIOTM Interface * JEDEC-standard pinout and package * Dual Double Data Rate interface * Byte Write controls sampled at data-in time * DLL circuitry for wide output data valid window and future frequency scaling * Burst of 2 Read and Write * 1.8 V +100/-100 mV core power supply * 1.5 V or 1.8 V HSTL Interface * Pipelined read operation * Fully coherent read and write pipelines * ZQ mode pin for programmable output drive strength * IEEE 1149.1 JTAG-compliant Boundary Scan * Pin-compatible with future 144Mb devices * 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package * RoHS-compliant 165-bump BGA package available
72Mb Burst of 2 DDR SigmaSIO-II SRAM
333 MHz-167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O
Bottom View
165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array JEDEC Std. MO-216, Variation CAB-1
SigmaRAMTM Family Overview
GS8662S08/09/18/36 are built in compliance with the SigmaSIO-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
Clocking and Addressing Schemes
A Burst of 2 SigmaSIO-II SRAM is a synchronous device. It employs dual input register clock inputs, K and K. The device also allows the user to manipulate the output register clock input quasi independently with dual output register clock inputs, C and C. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Each Burst of 2 SigmaSIO-II SRAM also supplies Echo Clock outputs, CQ and CQ, which are synchronized with read data output. When used in a source synchronous clocking scheme, the Echo Clock outputs can be used to fire input registers at the data's destination. Because Separate I/O Burst of 2 RAMs always transfer data in two packets, A0 is internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfer. Because the LSB is tied off internally, the address field of a Burst of 2 RAM is always one address pin less than the advertised index depth (e.g., the 4M x 18 has a 1M addressable index).
Parameter Synopsis
- 333 tKHKH tKHQV 3.0 ns 0.45 ns -300 3.3 ns 0.45 ns -250 4.0 ns 0.45 ns -200 5.0 ns 0.45 ns -167 6.0 ns 0.5 ns
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662S08/09/18/36E-333/300/250/200/167
8M x 8 SigmaQuad SRAM--Top View
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 SA NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK 3 SA NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 NW1 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC NW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC NC NC D2 NC NC VREF Q1 NC NC NC NC NC TMS 11 CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC NC TDI
11 x 15 Bump BGA--15 x 17 mm2 Body--1 mm Bump Pitch Notes: 1. NW0 controls writes to D0:D3. NW1 controls writes to D4:D7. 2. It is recommended that H1 be tied low for compatibility with future devices.
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Preliminary GS8662S08/09/18/36E-333/300/250/200/167
8M x 9 SigmaQuad SRAM--Top View
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 2 SA NC NC D5 NC NC D6 VREF NC NC Q7 NC D8 NC TCK 3 SA NC NC NC Q5 NC Q6 VDDQ NC NC D7 NC NC Q8 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 NC NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC NC NC D3 NC NC VREF Q2 NC NC NC NC D0 TMS 11 CQ Q4 D4 NC Q3 NC NC ZQ D2 NC Q1 D1 NC NC TDI
11 x 15 Bump BGA--15 x 17 mm2 Body--1 mm Bump Pitch Notes: 1. BW controls writes to D0:D7 1. It is recommended that H1 be tied low for compatibility with future devices.
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Preliminary GS8662S08/09/18/36E-333/300/250/200/167
4M x 18 SigmaQuad SRAM--Top View
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 VSS/SA (144Mb) Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK 3 SA D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW1 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
11 x 15 Bump BGA--15 x 17 mm2 Body--1 mm Bump Pitch Notes: 1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17. 2. It is recommended that H1 be tied low for compatibility with future devices.
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Preliminary GS8662S08/09/18/36E-333/300/250/200/167
2M x 36 SigmaQuad SRAM--Top View
1 A B C D E F G H J K L M N P R CQ Q27 D27 D28 Q29 Q30 D30 DOFF D31 Q32 Q33 D33 D34 Q35 TDO 2 VSS/SA (288Mb) Q18 Q28 D20 D29 Q21 D22 VREF Q31 D32 Q24 Q34 D26 D35 TCK 3 SA D18 D19 Q19 Q20 D21 Q22 VDDQ D23 Q23 D24 D25 Q25 Q26 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW2 BW3 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 BW1 BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 SA 10 VSS/SA (144Mb) Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
11 x 15 Bump BGA--15 x 17 mm2 Body--1 mm Bump Pitch Notes: 1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17. 2. BW2 controls writes to D18:D26. BW3 controls writes to D27:D35. 3. It is recommended that H1 be tied low for compatibility with future devices.
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Preliminary GS8662S08/09/18/36E-333/300/250/200/167
Pin Description Table Symbol
SA NC R/W NW0-NW1 BW0-BW1 BW0-BW3 K C TMS TDI TCK TDO VREF ZQ K C DOFF LD CQ CQ Dn Qn VDD VDDQ VSS
Description
Synchronous Address Inputs No Connect Read/Write Contol Pin Synchronous Nybble Writes Synchronous Byte Writes Synchronous Byte Writes Input Clock Output Clock Test Mode Select Test Data Input Test Clock Input Test Data Output HSTL Input Reference Voltage Output Impedance Matching Input Input Clock Output Clock DLL Disable Synchronous Load Pin Output Echo Clock Output Echo Clock Synchronous Data Inputs Synchronous Data Outputs Power Supply Isolated Output Buffer Supply Power Supply: Ground
Type
Input -- Input Input Input Input Input Input Input Input Input Output Input Input Input Output -- -- Output Output Input Output Supply Supply Supply
Comments
-- -- Write Active Low; Read Active High Active Low x08 Version Active Low x18 Version Active Low x36 Version Active High Active High -- -- -- -- -- -- Active Low Active Low Active Low Active Low Active Low Active High
1.8 V Nominal 1.8 or 1.5 V Nominal --
Notes: 1. C, C, K, or K cannot be set to VREF voltage. 2. When ZQ pin is directly connected to VDD, output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 3. NC = Not Connected to die or any other pin
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Preliminary GS8662S08/09/18/36E-333/300/250/200/167
Background
Separate I/O SRAMs, like SigmaQuad SRAMs, are attractive in applications where alternating reads and writes are needed. On the other hand, Common I/O SRAMs like the SigmaCIO family are popular in applications where bursts of read or write traffic are needed. The SigmaSIO SRAM is a hybrid of these two devices. Like the SigmaQuad family devices, the SigmaSIO features a separate I/O data path, offering the user independent Data In and Data Out pins. However, the SigmaSIO devices offer a control protocol like that offered on the SigmaCIO devices. Therefore, while SigmaQuad SRAMs allow a user to operate both data ports at the same time, they force alternating loads of read and write addresses. SigmaSIO SRAMs allow continuous loads of read or write addresses like SigmaCIO SRAMs, but in a separate I/O configuration. Like a SigmaQuad SRAM, a SigmaSIO-II SRAM can execute an alternating sequence of reads and writes. However, doing so results in the Data In port and the Data Out port stalling with nothing to do on alternate transfers. A SigmaQuad device would keep both ports running at capacity full time. On the other hand, the SigmaSIO device can accept a continuous stream of read commands and read data or a continuous stream of write commands and write data. The SigmaQuad device, by contrast, restricts the user from loading a continuous stream of read or write addresses. The advantage of the SigmaSIO device is that it allows twice the random address bandwidth for either reads or writes than could be acheived with a SigmaQuad version of the device. SigmaCIO SRAMs offer this same advantage, but do not have the separate Data In and Data Out pins offered on the SigmaSIO SRAMs. Therefore, SigmaSIO devices are useful in psuedo dual port SRAM applications where communication of burst traffic between two electrically independent busses is desired. Each of the three SigmaQuad Family SRAMs--SigmaQuad, SigmaCIO, and SigmaSIO--supports similar address rates because random address rate is determined by the internal performance of the RAM. In addition, all three SigmaQuad Family SRAMs are based on the same internal circuits. Differences between the truth tables of the different devices proceed from differences in how the RAM's interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to the application at hand. Burst of 2 Sigma SIO-II SRAM DDR Read The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A high on the R/W pin begins a read cycle. The two resulting data output transfers begin after the next rising edge of the K clock. Data is clocked out by the next rising edge of the C if it is active. Otherwise, data is clocked out at the next rising edge of K. The next data chunk is clocked out on the rising edge of C, if active. Otherwise, data is clocked out on the rising edge of K. Burst of 2 Sigma SIO-II SRAM DDR Write The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A low on the R/W pin, begins a write cycle. Data is clocked in by the next rising edge of K and then the rising edge of K.
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Preliminary GS8662S08/09/18/36E-333/300/250/200/167
Power-Up Sequence for SigmaQuad-II SRAMs SigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations. Power-Up Sequence
1. Power-up and maintain Doff at low state.
1a. 1b. 1c. Apply VDD. Apply VDDQ. Apply VREF (may also be applied at the same time as VDDQ).
2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high. 3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.
Note: If you want to tie Doff high with an unstable clock, you must stop the clock for a minimum of 30 seconds to reset the DLL after the clocks become stablized.
DLL Constraints
* The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (tKCVar on page 21). * The DLL cannot operate at a frequency lower than 119 MHz. * If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during the initial stage.
Power-Up Sequence (Doff controlled)
Power UP Interval Unstable Clocking Interval DLL Locking Interval (1024 Cycles) Normal Operation
K
K
VDD
VDDQ
VREF
Doff
Power-Up Sequence (Doff tied High)
Power UP Interval Unstable Clocking Interval Stop Clock Interval 30ns Min DLL Locking Interval (1024 Cycles) Normal Operation
K
K
VDD
VDDQ
VREF
Doff
Note: If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.
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Preliminary GS8662S08/09/18/36E-333/300/250/200/167
Special Functions
Byte Write and Nybble Write Control Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0-D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence. Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18 version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence. Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, "Nybble Write Enable" and "NWx" may be substituted in all the discussion above.
Example x18 RAM Write Sequence using Byte Write Enables Data In Sample Time
Beat 1 Beat 2
BW0
0 1
BW1
1 0
D0-D8
Data In Don't Care
D9-D17
Don't Care Data In
Resulting Write Operation Beat 1 D0-D8
Written
Beat 2 D0-D8
Unchanged
D9-D17
Unchanged
D9-D17
Written
Output Register Control SigmaSIO-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs.
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Preliminary GS8662S08/09/18/36E-333/300/250/200/167
Example Four Bank Depth Expansion Schematic
R/W3 LD3 R/W2 LD2 R/W1 LD1 R/W0 LD0 A0-An K D1-Dn Bank 0 A R/W LD K D C
C Q1-Qn Note: For simplicity BWn is not shown.
Bank 1 A R/W LD
Bank 2 A R/W LD
Bank 3 A R/W LD K
Q
K D C
Q
K D C
Q
D C
Q
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Preliminary GS8662S08/09/18/36E-333/300/250/200/167
Burst of 2 SigmaSIO-II SRAM Depth Expansion
Write B
K K Address LD Bank 1 LD Bank 2 R/W Bank 1 R/W Bank 2 BWx Bank 1 BWx Bank 2 B+1 D Bank 1 D Bank 2 C Bank 1 C Bank 1 Q Bank 1 CQ Bank 1 CQ Bank 1 C Bank 2 C Bank 2 Q Bank 2 CQ Bank 2 CQ Bank 2 C C+1 G G+1 J E E+1 H H+1 B D+1 D F F+1 B C D E F G H J
Read C
Write D
Read E
Write F
Read G
Read H
Read J
NOP
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Preliminary GS8662S08/09/18/36E-333/300/250/200/167
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaSIO-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a vendor-specified tolerance is between 150 and 300. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM's output impedance circuitry compensates for drifts in supply voltage and temperature every 1024 cycles. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. Impedance updates for "0s" occur whenever the SRAM is driving "1s" for the same DQs (and vice-versa for "1s") or the SRAM is in HI-Z.
Separate I/O Burst of 2 Sigma SIO-II SRAM Truth Table A K (tn)
X V V
LD K (tn)
1 0 0
R/W K (tn)
X 1 0
Current Operation K (tn)
Deselect Read Write
D K (tn+1)
X X D0
D K (tn+1)
-- -- D1
Q K (tn+1)
Hi-Z Q0 Hi-Z
Q K (tn+1)
-- Q1 --
Notes: 1. "1" = input "high"; "0" = input "low"; "V" = input "valid"; "X" = input "don't care" 2. "--" indicates that the input requirement or output state is determined by the next operation. 3. Q0 and Q1 indicate the first and second pieces of output data transferred during Read operations. 4. D0 and D1 indicate the first and second pieces of input data transferred during Write operations. 5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when preceded by a Read command. 6. CQ is never tristated. 7. Users should not clock in metastable addresses.
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Preliminary GS8662S08/09/18/36E-333/300/250/200/167
x18 Byte Write Clock Truth Table BW K (tn+1)
T T F F
BW K (tn+2)
T F T F
Current Operation K (tn)
Write Dx stored if BWn = 0 in both data transfers Write Dx stored if BWn = 0 in 1st data transfer only Write Dx stored if BWn = 0 in 2nd data transfer only Write Abort No Dx stored in either data transfer
D K (tn+1)
D1 D1 X X
D K (tn+2)
D2 X D2 X
Notes: 1. "1" = input "high"; "0" = input "low"; "X" = input "don't care"; "T" = input "true"; "F" = input "false". 2. If one or more BWn = 0, then BW = "T", else BW = "F".
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Preliminary GS8662S08/09/18/36E-333/300/250/200/167
x36 Byte Write Enable (BWn) Truth Table BW3
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
BW2 BW1 BW0
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
D27-D35
Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Data In Data In Data In Data In Data In Data In Data In Data In
D18-D26
Don't Care Don't Care Don't Care Don't Care Data In Data In Data In Data In Don't Care Don't Care Don't Care Don't Care Data In Data In Data In Data In
D9-D17
Don't Care Don't Care Data In Data In Don't Care Don't Care Data In Data In Don't Care Don't Care Data In Data In Don't Care Don't Care Data In Data In
D0-D8
Don't Care Data In Don't Care Data In Don't Care Data In Don't Care Data In Don't Care Data In Don't Care Data In Don't Care Data In Don't Care Data In
x8 Nybble Write Enable (NWn) Truth Table NW1 NW0
1 0 1 0 1 1 0 0
D9-D17
Don't Care Don't Care Data In Data In
D0-D8
Don't Care Data In Don't Care Data In
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Preliminary GS8662S08/09/18/36E-333/300/250/200/167
State Diagram
Power-Up
LOAD
NOP
LOAD
LOAD
Load New LOAD LOAD READ WRITE LOAD
DDR Read
DDR Write
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Preliminary GS8662S08/09/18/36E-333/300/250/200/167
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
VDD VDDQ VREF VI/O VIN IIN IOUT TJ TSTG
Description
Voltage on VDD Pins Voltage in VDDQ Pins Voltage in VREF Pins Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Maximum Junction Temperature Storage Temperature
Value
-0.5 to 2.9 -0.5 to VDD -0.5 to VDDQ -0.5 to VDDQ +0.3 ( 2.9 V max.) -0.5 to VDDQ +0.3 ( 2.9 V max.) +/-100 +/-100 125 -55 to 125
Unit
V V V V V mA dc mA dc
o o
C C
Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.
Recommended Operating Conditions Power Supplies Parameter
Supply Voltage I/O Supply Voltage Reference Voltage
Symbol
VDD VDDQ VREF
Min.
1.7 1.7 0.68
Typ.
1.8 1.8 --
Max.
1.9 1.9 0.95
Unit
V V V
Notes: 1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V VDDQ 1.6 V (i.e., 1.5 V I/O) and 1.7 V VDDQ 1.95 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case. 2. The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The power down sequence must be the reverse. VDDQ must not exceed VDD.
Operating Temperature Parameter
Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions)
Symbol
TA TA
Min.
0 -40
Typ.
25 25
Max.
70 85
Unit
C C
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Preliminary GS8662S08/09/18/36E-333/300/250/200/167
HSTL I/O DC Input Characteristics Parameter
DC Input Logic High DC Input Logic Low Note: Compatible with both 1.8 V and 1.5 V I/O drivers
Symbol
VIH (dc) VIL (dc)
Min
VREF + 0.1 -0.3
Max
VDDQ + 0.3 VREF - 0.1
Units
mV mV
Notes
1 1
HSTL I/O AC Input Characteristics Parameter
AC Input Logic High AC Input Logic Low VREF Peak to Peak AC Voltage
Symbol
VIH (ac) VIL (ac) VREF (ac)
Min
VREF + 0.2 -- --
Max
-- VREF - 0.2 5% VREF (DC)
Units
mV mV mV
Notes
3,4 3,4 1
Notes: 1. The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF. 2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other. 3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers. 4. See AC Input Definition drawing below.
HSTL I/O AC Input Definitions
VIH (ac) VREF VIL (ac)
Undershoot Measurement and Timing
VIH
Overshoot Measurement and Timing
20% tKHKH VDD + 1.0 V
VSS 50% VSS - 1.0 V 20% tKHKH
50% VDD
VIL
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Preliminary GS8662S08/09/18/36E-333/300/250/200/167
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 3.3 V)
Parameter
Input Capacitance Output Capacitance Note: This parameter is sample tested.
Symbol
CIN COUT
Test conditions
VIN = 0 V VOUT = 0 V
Typ.
4 6
Max.
5 7
Unit
pF pF
AC Test Conditions Parameter
Input high level Input low level Max. input slew rate Input reference level Output reference level Note: Test conditions as specified with output loading as shown unless otherwise noted.
Conditions
VDDQ 0V 2 V/ns VDDQ/2 VDDQ/2
AC Test Load Diagram
DQ 50 VT = VDDQ/2 RQ = 250 (HSTL I/O) VREF = 0.75 V
Input and Output Leakage Characteristics Parameter
Input Leakage Current (except mode pins) Doff Output Leakage Current
Symbol
IIL IINDOFF IOL
Test Conditions
VIN = 0 to VDD VDD VIN VIL 0 V VIN VIL Output Disable, VOUT = 0 to VDDQ
Min.
-2 uA -100 uA -2 uA -2 uA
Max
2 uA 2 uA 2 uA 2 uA
Notes
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Preliminary GS8662S08/09/18/36E-333/300/250/200/167
Programmable Impedance HSTL Output Driver DC Electrical Characteristics Parameter
Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage
Symbol
VOH1 VOL1 VOH2 VOL2
Min.
VDDQ/2 - 0.12 VDDQ/2 - 0.12 VDDQ - 0.2 Vss
Max.
VDDQ/2 + 0.12 VDDQ/2 + 0.12 VDDQ 0.2
Units
V V V V
Notes
1, 3 2, 3 4, 5 4, 6
Notes: 1. IOH = (VDDQ/2) / (RQ/5) +/- 15% @ VOH = VDDQ/2 (for: 175 RQ 350). 2. IOL = (VDDQ/2) / (RQ/5) +/- 15% @ VOL = VDDQ/2 (for: 175 RQ 350). 3. Parameter tested with RQ = 250 and VDDQ = 1.5 V or 1.8 V 4. Minimum Impedance mode, ZQ = VSS 5. IOH = -1.0 mA 6. IOL = 1.0 mA
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Operating Currents
-333 Parameter Symbol Test Conditions
0 to 70C TBD TBD TBD TBD -40 to 85C TBD TBD TBD TBD
-300
0 to 70C TBD TBD TBD TBD -40 to 85C TBD TBD TBD TBD
-250
0 to 70C TBD TBD TBD TBD -40 to 85C TBD TBD TBD TBD
-200
0 to 70C TBD TBD TBD TBD -40 to 85C TBD TBD TBD TBD
-167
0 to 70C TBD TBD TBD TBD -40 to 85C TBD TBD TBD TBD
Notes
Operating Current (x36): DDR Operating Current (x18): DDR Operating Current (x9): DDR Operating Current (x8): DDR
IDD IDD IDD IDD
VDD = Max, IOUT = 0 mA Cycle Time tKHKH Min VDD = Max, IOUT = 0 mA Cycle Time tKHKH Min VDD = Max, IOUT = 0 mA Cycle Time tKHKH Min VDD = Max, IOUT = 0 mA Cycle Time tKHKH Min Device deselected, IOUT = 0 mA, f = Max, All Inputs 0.2 V or VDD - 0.2 V
2, 3 2, 3 2, 3 2, 3
Standby Current (NOP): DDR
ISB1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
2, 4
Notes:
1. 2. 3. 4. Power measured with output pins floating. Minimum cycle, IOUT = 0 mA Operating current is calculated with 50% read cycles and 50% write cycles. Standby Current is only after all pending read and write burst operations are completed.
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Preliminary GS8662S08/09/18/36E-333/300/250/200/167
AC Electrical Characteristics
Parameter Clock
K, K Clock Cycle Time C, C Clock Cycle Time tTKC Variable K, K Clock High Pulse Width C, C Clock High Pulse Width K, K Clock Low Pulse Width C, C Clock Low Pulse Width K to K High C to C High K, K Clock High to C, C Clock High DLL Lock Time K Static to DLL reset tKHKH tCHCH tKCVar tKHKL tCHCL tKLKH tCLCH tKHKH tKHCH tKCLock tKCReset tKHQV tCHQV tKHQX tCHQX tKHCQV tCHCQV tKHCQX tCHCQX tCQHQV tCQHQX tKHQZ tCHQZ tKHQX1 tCHQX1 tAVKH tIVKH tDVKH 3.0 -- 1.2 1.2 1.35 0 1024 30 3.5 0.2 -- -- -- 1.3 -- -- 3.3 -- 1.32 1.32 1.49 0 1024 30 4.2 0.2 -- -- -- 1.45 -- -- 4.0 -- 1.6 1.6 1.8 0 1024 30 6.3 0.2 -- -- -- 1.8 -- -- 5.0 -- 2.0 2.0 2.2 0 1024 30 7.9 0.2 -- -- -- 2.3 -- -- 6.0 -- 2.4 2.4 2.7 0 1024 30 8.4 0.2 -- -- -- 2.8 -- -- ns ns ns ns ns ns cycle ns 6 5
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Units
Output Times
K, K Clock High to Data Output Valid C, C Clock High to Data Output Valid K, K Clock High to Data Output Hold C, C Clock High to Data Output Hold K, K Clock High to Echo Clock Valid C, C Clock High to Echo Clock Valid K, K Clock High to Echo Clock Hold C, C Clock High to Echo Clock Hold CQ, CQ High Output Valid CQ, CQ High Output Hold K Clock High to Data Output High-Z C Clock High to Data Output High-Z K Clock High to Data Output Low-Z C Clock High to Data Output Low-Z -- -0.45 -- -0.45 -- -0.25 -- -0.45 0.45 -- 0.45 -- 0.25 -- 0.45 -- -- -0.45 -- -0.45 -- -0.27 -- -0.45 0.45 -- 0.45 -- 0.27 -- 0.45 -- -- -0.45 -- -0.45 -- -0.30 -- -0.45 0.45 -- 0.45 -- 0.30 -- 0.45 -- -- -0.45 -- -0.45 -- -0.35 -- -0.45 0.45 -- 0.45 -- 0.35 -- 0.45 -- -- -0.5 -- -0.5 -- -0.40 -- -0.5 0.5 -- 0.5 -- 0.40 -- 0.5 -- ns ns ns ns ns ns ns ns 7 7 3 3 3 3
Setup Times
Address Input Setup Time Control Input Setup Time Data Input Setup Time 0.4 0.4 0.28 -- -- -- 0.4 0.4 0.3 -- -- -- 0.5 0.5 0.35 -- -- -- 0.6 0.6 0.4 -- -- -- 0.7 0.7 0.5 -- -- -- ns ns ns 2
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Notes
-333
-300
-250
-200
-167
Preliminary GS8662S08/09/18/36E-333/300/250/200/167
AC Electrical Characteristics (Continued)
Parameter Hold Times
Address Input Hold Time Control Input Hold Time Data Input Hold Time tKHAX tKHIX tKHDX 0.4 0.4 0.28 -- -- -- 0.4 0.4 0.3 -- -- -- 0.5 0.5 0.35 -- -- -- 0.6 0.6 0.4 -- -- -- 0.7 0.7 0.5 -- -- -- ns ns ns
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Units
Notes: 1. All Address inputs must meet the specified setup and hold times for all latching clock edges. 2. Control singles are R, W, BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36). 3. If C, C are tied high, K, K become the references for C, C timing parameters 4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70C, 1.7 V). It is not possible for two SRAMs on the same board to be at such different voltages and temperatures. 5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 6. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable. 7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a 0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard bands and test setup variations.
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Notes
-333
-300
-250
-200
-167
Preliminary GS8662S08/09/18/36E-333/300/250/200/167
K Controlled Read-First Timing Diagram
Read A KHKL KHKH K KH#KH K AVKH KHAX Address A IVKH LD IVKH R/W IVKH KHIX BWx B DVKH KHDX D KHQX1 Q CQ KHCQV KHCQX CQ CQHQV CQHQX A A+1 B B+1 KHQZ C KHQV C+1 D KHQX D+1 B+1 KHIX B KHIX C D E KLKH Write B Read C Read E Deselect Deselect
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K Controlled Write-First Timing Diagram
NOP Write A Read B KHKL KHKH K KH#KH K AVKH KHAX Address IVKH LD IVKH R/W KHIX IVKH BWx A A+1 KHDX DVKH D A A+1 D D+1 KHQV KHQX1 Q KHCQX KHCQV CQ KHCQX KHCQV CQ CQHQV CQHQX B B+1 KHQX C C+1 KHQZ E E+1 D D+1 E E+1 KHIX A KHIX B C D E KLKH Read C Write D Write E Deselect
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C Controlled Read-First Timing Diagram
Read A KHKL KHKH K KHKH# K AVKH KHAX Address A IVKH KHIX LD IVKH KHIX R/W KHIX IVKH BWx B B+1 KHDX DVKH D CLCH KHCH C CHCH# C CHQX1 Q CQ CHCQX CHCQV CQ CQHCV CQHQX A A+1 CHQZ C CHQV C+1 CHQX D D+1 CHCL CHCH B B+1 B C D KLKH Write B Read C Read D Deselect Deselect
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C Controlled Write-First Timing Diagram
NOP Write A Read B KHKL KHKH K KH#KH K KHAX AVKH Addr IVKH LD IVKH R/W KHIX IVKH BWx A A+1 KHDX DVKH D A A+1 KHKL KHKH C KH#KH C CHQX1 CHQX CHQV Q CQ CQHQV CQ CQHQX B B+1 CHQZ KLKH C C+1 D D+1 C C+1 D D+1 KHIX A KHIX B C D E KLKH Write C Write D Read E Deselect
JTAG Port Operation
Overview The JTAG Port on this RAM operates in a manner that is compliant with the current IEEE Standard, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDD. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
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JTAG Pin Descriptions Pin
TCK TMS
Pin Name
Test Clock Test Mode Select
I/O
In In
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.
TDI
Test Data In
In
TDO
Test Data Out
Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.
Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automatically at power-up. JTAG Port Registers Overview The various JTAG registers, referred to as Test Access Port or TAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM's JTAG Port to another device in the scan chain with as little delay as possible. Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM's input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
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Preliminary GS8662S08/09/18/36E-333/300/250/200/167
JTAG TAP Block Diagram
* * *
108
*
*
*
*
*
*
* *
1
Boundary Scan Register
0
Bypass Register
210
0
Instruction Register TDI ID Code Register
31 30 29
TDO
*
***
210
Control Signals TMS TCK Test Access Port (TAP) Controller
Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Bit # x36 x18 x9 x8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 0 0 011011001 0 011011001 0 011011001 0 011011001 0 1 1 1 1
Tap Controller Instruction Set
Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers.
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When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table.
JTAG Tap Controller State Diagram
1
Test Logic Reset
0 1 1 1
0
Run Test Idle
Select DR
0 1
Select IR
0 1
Capture DR
0
Capture IR
0
Shift DR
1 1
0 1
Shift IR
1
0
Exit1 DR
0
Exit1 IR
0
Pause DR
1
0
Pause IR
1
0
Exit2 DR
1
0
Exit2 IR
1
0
Update DR
1 0 1
Update IR
0
Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the Rev: 1.01 9/2005 29/37 (c) 2005, GSI Technology
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Preliminary GS8662S08/09/18/36E-333/300/250/200/167
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM's input pins; therefore, the RAM's internal state is still determined by its input pins. Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register's contents, in parallel, on the RAM's data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM's input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM's output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
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JTAG TAP Instruction Set Summary Instruction
EXTEST IDCODE SAMPLE-Z RFU SAMPLE/ PRELOAD RFU RFU BYPASS
Code
000 001 010 011 100 101 110 111
Description
Places the Boundary Scan Register between TDI and TDO. Preloads ID Register and places it between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. Do not use this instruction; Reserved for Future Use. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Do not use this instruction; Reserved for Future Use. Do not use this instruction; Reserved for Future Use. Places Bypass Register between TDI and TDO.
Notes
1 1, 2 1 1 1 1 1 1
Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state.
JTAG Port Recommended Operating Conditions and DC Characteristics Parameter
Power Supply Voltage Input High Voltage Input Low Voltage Output High Voltage (IOH = -2 mA) Output Low Voltage (IOL = 2 mA) Note: The input level of SRAM pin is to follow the SRAM DC specification.
Symbol
VDDQ VIH VIL VOH VOL
Min.
1.7 1.3 -0.3 1.4 VSS
Typ.
1.8 -- -- -- --
Max.
1.9 VDD + 0.3 0.5 VDD 0.4
Unit
V V V V V
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JTAG Port AC Test Conditions Parameter
Input High/Low Level Input Rise/Fall Time Input and Output Timing Reference Level Notes: 1. Distributed scope and test jig capacitance. 2. Test conditions as shown unless otherwise noted.
Symbol
VIH/VIL TR/TF
Min
1.3/0.5 1.0/1.0 0.9
Unit
V ns V
JTAG Port Timing Diagram
tTKC TCK tTH tTS TDI tTH tTS TMS tTKQ TDO tTH tTS Parallel SRAM input
tTKH
tTKL
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JTAG Port AC Electrical Characteristics
Parameter TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TMS Input Setup Time TMS Input Hold Time TDI Input Setup Time TDI Input Hold Time SRAM Input Setup Time SRAM Input Hold Time Clock Low to Output Valid Symbol tCHCH tCHCL tCLCH tMVCH tCHMX tDVCH tCHDX tSVCH tCHSX tCLQV Min. 50 20 20 5 5 5 5 5 5 0 Max -- -- -- -- -- -- -- -- -- 10 Unit ns ns ns ns ns ns ns ns ns ns
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Package Dimensions--165-Bump FPBGA (Package E)
A1 CORNER
TOP VIEW
BOTTOM VIEW O0.10 M C O0.25 M C A B O0.40~0.60 (165x)
A1 CORNER
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R
11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R
1.0 10.0 B 0.20(4x) 150.05 1.0
170.05
14.0
A
Rev: 1.01 9/2005
0.36~0.46 1.50 MAX.
C
SEATING PLANE
0.20 C
34/37
1.0
1.0
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Preliminary GS8662S08/09/18/36E-333/300/250/200/167
Ordering Information--GSI SigmaSIO-II SRAM Org
2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9
Part Number1
GS8662S36E-333 GS8662S36E-300 GS8662S36E-250 GS8662S36E-200 GS8662S36E-167 GS8662S36E-333I GS8662S36E-300I GS8662S36E-250I GS8662S36E-200I GS8662S36E-167I GS8662S18E-333 GS8662S18E-300 GS8662S18E-250 GS8662S18E-200 GS8662S18E-167 GS8662S18E-333I GS8662S18E-300I GS8662S18E-250I GS8662S18E-200I GS8662S18E-167I GS8662S09E-333 GS8662S09E-300 GS8662S09E-250 GS8662S09E-200 GS8662S09E-167 GS8662S09E-333I GS8662S09E-300I GS8662S09E-250I GS8662S09E-200I
Type
SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM
Package
165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA
Speed (MHz)
333 300 250 200 167 333 300 250 200 167 333 300 250 200 167 333 300 250 200 167 333 300 250 200 167 333 300 250 200
TA3
C C C C C I I I I I C C C C C I I I I I C C C C C I I I I
Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS866x36E-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. Rev: 1.01 9/2005 35/37 (c) 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662S08/09/18/36E-333/300/250/200/167
Ordering Information--GSI SigmaSIO-II SRAM Org
8M x 9 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18
Part Number1
GS8662S09E-167I GS8662S08E-333 GS8662S08E-300 GS8662S08E-250 GS8662S08E-200 GS8662S08E-167 GS8662S08E-333I GS8662S08E-300I GS8662S08E-250I GS8662S08E-200I GS8662S08E-167I GS8662S36GE-333 GS8662S36GE-300 GS8662S36GE-250 GS8662S36GE-200 GS8662S36GE-167 GS8662S36GE-333I GS8662S36GE-300I GS8662S36GE-250I GS8662S36GE-200I GS8662S36GE-167I GS8662S18GE-333 GS8662S18GE-300 GS8662S18GE-250 GS8662S18GE-200 GS8662S18GE-167 GS8662S18GE-333I GS8662S18GE-300I GS8662S18GE-250I GS8662S18GE-200I
Type
SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM
Package
165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA
Speed (MHz)
167 333 300 250 200 167 333 300 250 200 167 333 300 250 200 167 333 300 250 200 167 333 300 250 200 167 333 300 250 200
TA3
I C C C C C I I I I I C C C C C I I I I I C C C C C I I I I
Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS866x36E-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
Rev: 1.01 9/2005
36/37
(c) 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS8662S08/09/18/36E-333/300/250/200/167
Ordering Information--GSI SigmaSIO-II SRAM Org
4M x 18 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 9 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8 8M x 8
Part Number1
GS8662S18GE-167I GS8662S09GE-333 GS8662S09GE-300 GS8662S09GE-250 GS8662S09GE-200 GS8662S09GE-167 GS8662S09GE-333I GS8662S09GE-300I GS8662S09GE-250I GS8662S09GE-200I GS8662S09GE-167I GS8662S08GE-333 GS8662S08GE-300 GS8662S08GE-250 GS8662S08GE-200 GS8662S08GE-167 GS8662S08GE-333I GS8662S08GE-300I GS8662S08GE-250I GS8662S08GE-200I GS8662S08GE-167I
Type
SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM SigmaSIO-II SRAM
Package
RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA RoHS-compliant 165-bump BGA
Speed (MHz)
167 333 300 250 200 167 333 300 250 200 167 333 300 250 200 167 333 300 250 200 167
TA3
I C C C C C I I I I I C C C C C I I I I I
Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS866x36E-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
SigmaSIO-II Revision History File Name
8662Sxx_r1 8662Sxx_r1; 8662Sxx_r1_01 Content
Format/Content
Description of changes
Creation of datasheet Added RoHS-compliant package information
Rev: 1.01 9/2005
37/37
(c) 2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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